The present invention relates to memory devices and methods for forming the same, and more specifically to non-volatile memory devices and methods for forming the same.
The flash memory device is an electrically programmable non-volatile memory device capable of programming in units of pages or multi-bits and erasing in units of blocks or sectors, thereby having excellent characteristics in respect of speed. The flash memory may be used in various devices such as a digital cellular phone, a digital camera, a LAN-switch, a PC card of a notebook computer, a digital set-top box, a built-in controller, etc.
As well known, the flash memory device comprises a source/drain, a tunneling oxide layer, a floating gate, a block insulating layer and a control gate. When a proper bias voltage is applied to the control gate, the source/drain and the substrate, the floating gate is charged or discharged to program or erase to have two different threshold voltages, corresponding to two logic levels.
Also, the semiconductor device should have been highly integrated so as to maintain high performance, high speed, low power dissipation and low production cost. Programming or erasing operation of the flash memory device is performed by injecting charge into the floating gate or rejecting charge therefrom through a tunneling insulating layer. The floating gate can be charged or discharged using Fouler-Nordheim tunneling (F-N tunneling) or channel-hot-carrier injection. In F-N tunneling, a large voltage is applied between the control gate and the substrate resulting in charge accumulating in the floating gate. If the tunneling insulating layer is too thin, charge tunnels the thin tunneling insulating layer at below the programming voltage or even without an external bias voltage. Accordingly, such restriction to the thickness of the tunnel oxide layer serves as an obstacle to achieve a high integration density.
Recently, there has been provided a flash memory device having a multi-gate structure where a plurality of channels are formed, for example, a double gate structure and a triple gate structure.
A flash memory device of multi-gate structure using a silicon fin and a method of forming the same are disclosed in Korea Patent No. 10-0420070. The flash memory device is schematically illustrated in FIGS. 1A and 1B. Reference number 2b in FIGS. 1A and 1B indicates a bulk silicon substrate, reference number 4 indicates a fin active region, reference number 6 indicates a first oxide layer, reference number 10 indicates a second oxide layer, reference number 12 indicates a tunneling oxide layer, reference number 16 indicates a control electrode, reference number 32 indicates a storage electrode, and reference number 34 indicates an oxide layer between electrodes.
However, according to the Korea Patent No. 10-0420070, when the control electrode 16 is defined using photolithography, the fin active region 4 and the tunneling oxide layer 12 can be attacked. If the tunneling oxide layer 12 is attacked deeply, a data retention characteristic of the flash memory device is degraded and the device reliability can not be ensured.
In addition, neighboring control electrodes can be electrically connected, since the control gate is formed crossing over a fin active region 4 having a protruding structure. Accordingly, when over-etching is performed to prevent electrical connection between neighboring control electrodes, sidewalls of silicon fins used as a channel region can be attacked by the etching.